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last digit is preserved in R+1 so that the entire result can be later handled as
eight-digit data.
TR 0
MOV(21)
#0001
DM 0101
00002
CLC(41)
ADD(30)
LR 25
#6103
DM 0100
MOV(21)
#0000
DM 0101
25504
25504
Address Instruction Operands
00000 LR 00002
00001 OUT TR 0
00002 CLC(41)
00003 AND(30)
LR 25
# 6103
DM 0100
00004 AND 25504
00005 MOV(21)
# 0001
DM 0101
00006 LD TR 0
00007 AND NOT 25504
00008 MOV(21)
# 0000
DM 0101
Although two ADD(30) can be used together to perform eight-digit BCD addi-
tion, ADDL(54) is designed specifically for this purpose.
5-17-6 DOUBLE BCD ADD – ADDL(54)
Au: First augend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Ad: First addend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Ladder Symbols
Operand Data Areas
R: First result word
IR, AR, DM, HR, LR
ADDL(54)
Au
Ad
R
@ADDL(54)
Au
Ad
R
When the execution condition is OFF, ADDL(54) is not executed. When the
execution condition is ON, ADDL(54) adds the contents of CY to the 8-digit
value in Au and Au+1 to the 8-digit value in Ad and Ad+1, and places the re-
sult in R and R+1. CY will be set if the result is greater than 99999999.
Au + 1 Au
Ad + 1 Ad
R + 1 R
+
CY
CY
Description
BCD Calculations Section 5-17
- (CPU01-E/03-E/11-E) 1
- OMRON Product References 2
- Visual Aids 2
- TABLE OF CONTENTS 3
- About this Manual: 6
- PRECAUTIONS 7
- 1 Intended Audience 8
- 2 General Precautions 8
- 3 Safety Precautions 8
- 5 Application Precautions 9
- 5Application Precautions 10
- SECTION 1 12
- Introduction 12
- 1-1 Overview 13
- 1-2 The Origins of PC Logic 13
- 1-3 PC Terminology 14
- 1-4 OMRON Product Terminology 15
- 1-5 Overview of PC Operation 15
- 1-6 Peripheral Devices 16
- 1-7 Available Manuals 18
- 1-8 LSS Capabilities 19
- 1-8-2 Online Operations 20
- LSS Capabilities Section 1-8 21
- SECTION 2 22
- Hardware Considerations 22
- 2-1 Indicators 23
- 2-2 PC Configuration 23
- PC Configuration Section 2-2 24
- SECTION 3 25
- Memory Areas 25
- 3-1 Introduction 26
- 3-2 Data Area Structure 26
- Bit number 27
- IR word 000 0000000000000000 27
- IR word 001 0000000000000000 27
- 3-3 IR (Internal Relay) Area 28
- IR Area Section 3-3 29
- 3-4 SR (Special Relay) Area 30
- SR Area Section 3-4 31
- 3-4-1 Remote I/O Systems 32
- Host Link Systems 33
- PC Link Systems 35
- 3-4-4 I/O Status Hold Bit 38
- 3-4-5 Output OFF Bit 39
- 3-4-12 Step Flag 41
- 3-4-14 Arithmetic Flags 41
- AR Area Section 3-5 42
- (CPU11-E only) 45
- 3-5-8 Power-OFF Counter 46
- 3-6 DM (Data Memory) Area 48
- DM Area Section 3-6 49
- 3-7 HR (Holding Relay) Area 50
- 3-8 TC (Timer/Counter) Area 50
- 3-9 LR (Link Relay) Area 51
- 3-10 Program Memory 52
- SECTION 4 53
- 4-1 Basic Procedure 54
- 4-2 Instruction Terminology 54
- 4-3 Basic Ladder Diagrams 55
- 4-3-2 Mnemonic Code 56
- 4-3-3 Ladder Instructions 57
- A LOAD instruction 58
- A LOAD NOT instruction 58
- 4-3-4 OUTPUT and OUTPUT NOT 60
- 4-3-5 The END Instruction 60
- Program execution 61
- Instruction 62
- 00000 00001 62
- 00002 00003 62
- 4-4 The Programming Console 68
- 4-4-1 The Keyboard 69
- 4-4-2 PC Modes 70
- 4-5 Preparation for Operation 72
- 4-5-2 Buzzer 73
- 4-5-3 Clearing Memory 73
- 4-5-5 Clearing Error Messages 76
- 4-5-6 Verifying the I/O Table 76
- 4-5-7 Reading the I/O Table 77
- 4-5-8 Clearing the I/O Table 79
- 4-5-9 NET Link Table Transfer 80
- 4-6-3 Checking the Program 86
- 4-6-5 Program Searches 89
- Original Program 91
- Diagram A: Correct Operation 93
- 4-6-8 Jumps 97
- 4-7 Controlling Bit Status 99
- Work Bits Section 4-8 100
- 4-9 Programming Precautions 102
- Diagram A: Incorrect 103
- Diagram B 103
- Diagram A 103
- 4-10 Program Execution 104
- Instruction Set 105
- SECTION 5 105
- 5-1 Notation 107
- 5-2 Instruction Format 107
- *DM 0001 108
- 5-6-2 AND LOAD and OR LOAD 113
- 5-7 Bit Control Instructions 114
- IR, AR, HR, LR 115
- 5-7-3 KEEP – KEEP(11) 116
- S execution condition 117
- R execution condition 117
- Status of B 117
- N: Jump number 120
- # (00 to 99) 120
- 5-10 END – END(01) 121
- 5-11 NO OPERATION – NOP(00) 122
- 5-12-1 TIMER – TIM 123
- N: TC number 127
- # (000 through 015 preferred) 127
- SV: Set value (word, BCD) 127
- IR, AR, DM, HR, LR, # 127
- 5-12-3 COUNTER – CNT 128
- # (000 through 511) 131
- 5-13 Data Shifting 133
- Data Shifting Section 5-13 134
- 5-13-5 ROTATE LEFT – ROL(27) 138
- 5-13-6 ROTATE RIGHT – ROR(28) 138
- 5-13-9 WORD SHIFT – WSFT(16) 140
- 5-14 Data Movement 142
- 5-14-2 MOVE NOT – MVN(22) 143
- Data Movement Section 5-14 144
- 5-14-5 BLOCK SET – BSET(71) 145
- 5-14-10 MOVE BIT – MOVB(82) 149
- 5-14-11 MOVE DIGIT – MOVD(83) 150
- 5-15 Data Comparison 151
- 5-15-2 COMPARE – CMP(20) 152
- Data Comparison Section 5-15 153
- 5-16 Data Conversion 159
- Data Conversion Section 5-16 160
- 5-17 BCD Calculations 172
- 5-17-1 INCREMENT – INC(38) 173
- 5-17-2 DECREMENT – DEC(39) 173
- 5-17-3 SET CARRY – STC(40) 173
- 5-17-4 CLEAR CARRY – CLC(41) 174
- 5-17-5 BCD ADD – ADD(30) 174
- BCD Calculations Section 5-17 175
- 5-17-7 BCD SUBTRACT – SUB(31) 176
- 5-17-9 BCD MULTIPLY – MUL(32) 181
- 5-17-11 BCD DIVIDE – DIV(33) 182
- 5-18 Binary Calculations 189
- Mi – Su – CY CY R 191
- 5-19 Logic Instructions 194
- 5-19-2 LOGICAL AND – ANDW(34) 195
- 5-19-3 LOGICAL OR – ORW(35) 195
- 5-20-1 Overview 197
- N: Subroutine number 198
- 5-21 Step Instructions 203
- Step controlled by LR 2000 204
- Step controlled by LR 2001 204
- Examples 205
- 5-22 Special Instructions 212
- 5-22-2 CYCLE TIME – SCAN(18) 213
- FAL(06) 00 215
- 5-22-6 SET SYSTEM – SYS(49) 216
- 5-22-7 BIT COUNTER – BCNT(67) 217
- Input data, x Result data 218
- Control Data 221
- SEND(90) 222
- RECV(98) 224
- SECTION 6 228
- Program Execution Timing 228
- 6-1 Cycle Time 229
- Cycle Time Section 6-1 230
- 6-1-2 CPU11-E Cycle Time 233
- 6-2 Calculating Cycle Time 235
- 6-2-2 PC with Link Units 236
- ÷ constant b word 239
- ÷ *DM b *DM 239
- ÷ word b word 240
- ÷ word b word (equals 0) 241
- 6-4 I/O Response Time 243
- I/O Response Time Section 6-4 244
- SECTION 7 245
- 7-1-1 Bit/Digit Monitor 246
- 7-1-2 Forced Set/Reset 249
- Word currently 252
- [ Data ] 252
- 7-1-6 3-word Monitor 254
- 3 words currently 255
- 7-1-8 Binary Monitor 256
- Indicates Force Reset 257
- Indicates Force Set 257
- Key Sequence 258
- IR bit 00115 IR bit 00100 259
- Returns to original display 261
- Current SV (during 261
- SV before the change 261
- SECTION 8 270
- Troubleshooting 270
- 8-1 Alarm Indicators 271
- 8-4 Error Messages 272
- Error Messages Section 8-4 273
- 8-5 Error Flags 275
- Error Flags Section 8-5 276
- Appendix A 277
- C200H I/O Units 278
- C200H Special I/O Units 279
- C200H Link Units 280
- Optional Products 281
- Optical Units 282
- Link Adapters 282
- DIN Products 282
- Optical Fiber Cable 283
- Cable Length 283
- Peripheral Devices 284
- Ladder Support Software (LSS) 284
- Appendix AStandard Models 285
- Appendix B 286
- Instruction Execution Times 289
- Basic Instructions 294
- Data Areas 295
- Special Instructions 296
- ≤ S ≤ Upper limit 1 308
- (SBs+Of) (D) 313
- Appendix C 319
- System Operations 320
- Programming Operations 322
- Cassette Tape Operations 327
- Appendix D 329
- Appendix E 332
- Dedicated Bits 333
- Appendix EData Areas 334
- AR Word Allocations 334
- AR Bit Allocations 334
- Data Areas Appendix E 335
- Appendix F 336
- I/O Bits 337
- Work Bits 338
- Data Storage 339
- Timers and Counters 340
- Appendix G 341
- Program Coding Sheet 342
- Appendix H 343
- Appendix I 344
- Glossary 345
- Revision History 367
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